/**
  ******************************************************************************
  * @file    Libraries/Device/TS32F020X/ts32f020x.h
  * @author  JUSHENG Application Team
  * @version V1.0.0
  * @date    02-19-2022
  * @brief   CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
  *          This file contains all the peripheral register's definitions, bits
  *          definitions and memory mapping for ts32f020x Connectivity line.
  *          The file is the unique include file that the application programmer
  *          is using in the C source code, usually in main.c. This file contains:
  *           - Data structures and the address mapping for all peripherals
  *           - Peripheral's registers declarations and bits definition
  *           - Macros to access peripherals registers hardware
  *
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; COPYRIGHT 2022 JUSHENG</center></h2>
  *
  *
  *
  ******************************************************************************
  */ 

/** @addtogroup CMSIS
  * @{
  */

/** @addtogroup TS32F020X
  * @{
  */

#ifndef __TS32F020X_H
#define __TS32F020X_H

#ifdef __cplusplus
 extern "C" {
#endif

/* Includes ------------------------------------------------------------------*/
#include "typedef.h"
     
/* Macro Definitions */
#if defined(__CC_ARM)                /* KEIL Compiler */
    #pragma anon_unions
    #define WEAK            __attribute__ ((weak))
    #define ALIAS(f)        __attribute__ ((weak, alias(#f)))
    #define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
                void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
    #define AT(n)           __attribute__((at(n)))
    #define NO_INIT         __attribute__((zero_init))
    #define USED            __attribute__((used))
#elif defined(__GNUC__)              /* GCC Compiler */
    #define WEAK            __attribute__ ((weak))
    #define ALIAS(f)        __attribute__ ((weak, alias(#f)))
    #define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
                void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
    #define AT(n)           __attribute__((at(n)))
    #define NO_INIT         __attribute__((zero_init))
    #define USED            __attribute__((used))
#elif defined (__ICCARM__)           /* IAR Compiler */
    #define _WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) weak __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS)
    #define __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) FUN=FUN_ALIAS
    #define WEAK            _Pragma("weak")
    #define ALIAS(f)        _Pragma(_STRINGIFY(weak f))
    #define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
                void FUN(void) _Pragma(_STRINGIFY(_WEAK_ALIAS_FUNC(FUN, FUN_ALIAS)));
    #define AT(n)           @(n)
    #define NO_INIT         __no_init
    #define USED            __root
#endif

/** 
  * @brief  device defines  
  */
#define __NVIC_PRIO_BITS           4U       /*!<  uses 4 Bits for the Priority Levels         */
#define __Vendor_SysTickConfig     0U       /*!< Set to 1 if different SysTick Config is used */
     
/** @addtogroup bitband
  * @brief \@0x2000_0000 - 0x200F-FFFF
            @0x4000_0000 - 0x400F-FFFF
  * @{
  */
//#define BITBAND_RAM(addr, bit) (*((uint32_t volatile*)(0x22000000u + (((uint32_t)&(addr) - (uint32_t)0x20000000u)<<5) + (((uint32_t)(bit))<<2))))
//#define BITBAND_REG(addr, bit) (*((uint32_t volatile*)(0x42000000u + (((uint32_t)&(addr) - (uint32_t)0x40000000u)<<5) + (((uint32_t)(bit))<<2))))

/**
  * @}
  */

/** @addtogroup Peripheral_registers_structures
  * @{
  */
     
/**
 * @brief TS32F020X Interrupt Number Definition, according to the selected device
 *        in @ref Library_configuration_section
 */
typedef enum IRQn {
/******  Cortex-M0 Processor Exceptions Numbers ***********************************************/
    NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                           */
    HardFault_IRQn              = -13,      /*!< 11 Cortex-M0 hard fault Interrupt            */
    BusFault_IRQn               = -11, 
    SVCall_IRQn                 = -5,       /*!< 11 Cortex-M0 SV Call Interrupt               */
    PendSV_IRQn                 = -2,       /*!< 14 Cortex-M0 Pend SV Interrupt               */
    SysTick_IRQn                = -1,       /*!< 15 Cortex-M0 System Tick Interrupt           */

/******  Peripheral Interrupt Numbers *************************************************************/
    LVD_IRQn                    = 0,
//    TKIRQ_IRQn                = 1,
    TKSCDN_IRQn                 = 2,
//    TKOVFL_IRQn               = 3,
    UART0_IRQn                  = 4,
    UART1_IRQn                  = 5,
    UST0_IRQn                   = 6,
    SPI0_IRQn                   = 7,
    GPIOA_IRQn                  = 8,
    GPIOB_IRQn                  = 9,
    WKPND_IRQn                  = 10,
    TIM0_IRQn                   = 11,
    TIM1_IRQn                   = 12,
    TIM4_IRQn                   = 13,
    ADC_IRQn                    = 14,
    CRC_DMA_IRQn                = 15,
    WDT_IRQn                    = 16,
    LCD_IRQn                    = 17,
} IRQn_Type;

/**
  * @}
  */
#include "core_cm0.h" 

/** @addtogroup Peripheral_registers_structures
  * @{
  */

/**
  * @brief Universal Synchronous Asynchronous Receiver Transmitter
  */
typedef struct {
    __IO uint32_t CON;
    __IO uint32_t BAUD;
    __IO uint32_t DATA;
    __IO uint32_t STA;
//    __IO uint32_t TSTADR;
//    __IO uint32_t RSTADR;
//    __IO uint32_t TDMALEN;
//    __IO uint32_t RDMALEN;
//    __IO uint32_t TDMACNT;
//    __IO uint32_t RDMACNT;
//    __IO uint32_t DMACON;
//    __IO uint32_t DMASTA;
//    __IO uint32_t RESERVED0;
//    __IO uint32_t RESERVED1;
//    __IO uint32_t RESERVED2;
//    __IO uint32_t MLCON;
} UART_TypeDef;


/**
  * @brief Serial Peripheral Interface
  */
typedef struct {
    __IO uint32_t CON0;
    __IO uint32_t CON1;
    __IO uint32_t CMD_DATA;
    __IO uint32_t BAUD;
    __IO uint32_t DMA_LEN;
    __IO uint32_t DMA_CNT;
    __IO uint32_t RESERVED0;
    __IO uint32_t STA;
} SPI_IIC_TypeDef;

/**
  * @brief Serial Peripheral Interface
  */
typedef struct {
    __IO uint32_t UST_MODE;
    __IO uint32_t UST_CON0;
    __IO uint32_t UST_DATA;
    __IO uint32_t UST_BAUD;
    __IO uint32_t UST_PRD_BUF;
    __IO uint32_t UST_CMP01;
    __IO uint32_t UST_CMP01_BUF;
    __IO uint32_t UST_CMP23;
    __IO uint32_t UST_CMP23_BUF;
    __IO uint32_t UST_CNT;
    __IO uint32_t UST_STA;
} UST_TypeDef;


/**
  * @brief WDT
  */
typedef struct {
    __IO uint32_t WDTCON;
    __IO uint32_t WDTKEY;
} WDT_TypeDef;

/**
  * @brief Frac PLL 0 (huge-ic)
  */
typedef struct {
    __IO uint32_t FPLL_CON;
    __IO uint32_t FPLL_INT;
    __IO uint32_t RESERVED0;
    __IO uint32_t FPLL_SSC;
} FPLL_TypeDef;

/**
  * @brief TIMERs
  */
typedef struct {
    __IO uint32_t TMR_CON;
    __IO uint32_t TMR_EN;
    __IO uint32_t TMR_IE;
    __IO uint32_t TMR_CNT;
    __IO uint32_t TMR_FLG;
    __IO uint32_t TMR_CLR;
    __IO uint32_t TMR_CAP1;
    __IO uint32_t TMR_CAP2;
    __IO uint32_t TMR_CAP3;
} TIMER_TypeDef;

typedef struct {
    __IO uint32_t TMR_ALLCON;
}TIMER_ALL_TypeDef;

//typedef struct {
//    __IO uint32_t TMR_DCTL;
//    __IO uint32_t TMR_DADR;
//    __IO uint32_t TMR_DLEN;
//    __IO uint32_t TMR_DCNT;
//    __IO uint32_t TMR_DMAIR0;
//    __IO uint32_t TMR_DMAIR1;
//} TIMER1_DMA_TypeDef;

/**
  * @brief EPWM
  */
//typedef struct {
//    __IO uint32_t TBCTL;
//    __IO uint32_t TBPRD;
//    __IO uint32_t TBPHASE;
//    __IO uint32_t CMPCTL;
//    __IO uint32_t CMPA;
//    __IO uint32_t CMPB;
//    __IO uint32_t CMPC;
//    __IO uint32_t CMPD;
//    __IO uint32_t AQCTLAB;
//    __IO uint32_t AQSFRC;
//    __IO uint32_t AQCSFRC;
//    __IO uint32_t DBCTL;
//    __IO uint32_t DBDELAY;
//    __IO uint32_t ETCTL;
//    __IO uint32_t ETCTL2;
//    __IO uint32_t ETFLAG;
//    __IO uint32_t DCCTL;
//    __IO uint32_t DCTRIPSEL;
//    __IO uint32_t BLANKOFFSET;
//    __IO uint32_t WINWIDTH;
//    __IO uint32_t TZCTL;
//    __IO uint32_t TZFLAG;
//    __IO uint32_t DCCAP;
//} EPWM_CH_TypeDef;

//typedef struct {
//    EPWM_CH_TypeDef CH[4];
//    __IO uint32_t TTCTL;
//} EPWM_TypeDef;

typedef struct {
    __IO uint32_t CFG;
    __IO uint32_t CR;
    __IO uint32_t CHS;
    __IO uint32_t STA;
    __IO uint32_t DATA;
    __IO uint32_t DMAADR;
    __IO uint32_t DMACNT;
    __IO uint32_t DMALEN;
    __IO uint32_t OFFSET;
    __IO uint32_t BOUND;
} ADC_TypeDef;

/**
  * @brief CRC
  */
typedef struct {
    __IO uint32_t CRC_CFG;
    __IO uint32_t CRC_INIT;
    __IO uint32_t CRC_INV;
    __IO uint32_t CRC_POLY;
    __IO uint32_t CRC_KST;
    __IO uint32_t CRC_STA;
    __IO uint32_t DMA_ADDR;
    __IO uint32_t DMA_LEN;
    __IO uint32_t CRC_OUT;
} CRC_TypeDef;

/**
  * @brief QEI
  */
//typedef struct {
//    __IO uint32_t QEICON;
//    __IO uint32_t DFLTCON;
//    __IO uint32_t POSCNT;
//    __IO uint32_t MAXCNT;
//    __IO uint32_t QEIE;
//    __IO uint32_t QEIFLAG;
//    __IO uint32_t QEICLR;
//    __IO uint32_t QEIO;
//    __IO uint32_t QEI_TIMER_PERIOD;
//    __IO uint32_t QEI_TIMER_CNT;
//    __IO uint32_t QEI_TIMER_CNT_LATCH;
//    __IO uint32_t QEI_ROTATE_PERIOD;
//    __IO uint32_t QEI_ROTATE_CNT;
//    __IO uint32_t QEI_ROTATE_CNT_LATCH;
//    __IO uint32_t POSCNT_LATCH;
//} QEI_TypeDef;

/**
  * @brief SYS_CTRL
  */
typedef struct {
    __IO uint32_t SYS_KEY;
    __IO uint32_t SYS_CON0;
    __IO uint32_t SYS_CON1;
    __IO uint32_t SYS_CON2;
    __IO uint32_t SYS_CON3;
    __IO uint32_t SYS_CON4;
    __IO uint32_t SYS_CON5;
    __IO uint32_t SYS_CON6;
    __IO uint32_t SYS_CON7;
    __IO uint32_t CLK_CON0;
    __IO uint32_t CLK_CON1;
    __IO uint32_t CLK_CON2;
    __IO uint32_t CLK_CON3;
    __IO uint32_t CLK_CON4;
    __IO uint32_t CLK_CON5;
    __IO uint32_t CLK_CON6;
    __IO uint32_t CLK_CON7;
    __IO uint32_t HOSC_MNT;
    __IO uint32_t SYS_ERR0;
    __IO uint32_t WKUP_CON0;
    __IO uint32_t LP_CON0;
    __IO uint32_t MBIST_CON0;
    __IO uint32_t MBIST_MISR;
    __IO uint32_t CHIP_IDCN;
    __IO uint32_t MODE_REG;
    __IO uint32_t PMU_CON0;
    __IO uint32_t RPCON;
    __IO uint32_t PMUBK;
    __IO uint32_t WKUP_CON1;
    __IO uint32_t RESERVED0[4];
    __IO uint32_t FLS_NVR00;
    __IO uint32_t FLS_NVR04;
    __IO uint32_t FLS_NVR14;
    __IO uint32_t FLS_NVR24;
    __IO uint32_t FLS_SYS20;
} SYSCTRL_TypeDef;

/**
  * @brief GPIO controller
  */
typedef struct {
    __IO uint32_t MODE;
    __IO uint32_t OTYPE;
    __IO uint32_t OSPEEDL;
    __IO uint32_t OSPEEDH;
    __IO uint32_t PUPD;
    __IO uint32_t IDAT;
    __IO uint32_t ODAT;
    __IO uint32_t BSR;
    __IO uint32_t RESERVED0;
    __IO uint32_t AFR[2];
    __IO uint32_t TGL;
    __IO uint32_t IMK;
    __IO uint32_t TGPEND;
    __IO uint32_t IE_EN;
    __IO uint32_t TG_EDGE;
} GPIO_TypeDef;

/**
  * @brief DIV controller
  */
//typedef struct {
//    __IO uint32_t DVDR;
//    __IO uint32_t DVSR;
//    __IO uint32_t DVQUO;
//    __IO uint32_t DVREM;
//    __IO uint32_t SR;
//    __IO uint32_t DVCON;
//} DIV_TypeDef;

/**
  * @brief SQRT controller
  */
//typedef struct {
//    __IO uint32_t SQRT_IN;
//} SQRT_TypeDef;

/**
  * @brief SQRT controller
*/
//typedef struct {
//    __IO uint32_t HWSDCON;
//    __IO uint32_t HWSDA;
//    __IO uint32_t HWSDB;
//    __IO uint32_t HWSDLMT1;
//    __IO uint32_t HWSDLMT2;
//    __IO uint32_t HWSDADD;
//} HWSD_TypeDef;


/**
  * @brief eFlash
  */
typedef struct {
    __IO uint32_t CTRLR0;               /*!< EFLASH control register,                 RW,  Address offset: 0x240  */
    __IO uint32_t KST;                  /*!< EFLASH kick start register,              RO,  Address offset: 0x244  */
    __IO uint32_t DONE;                 /*!< EFLASH finish flag register,             RO,  Address offset: 0x248  */
    __IO uint32_t PROG_ADDR;            /*!< EFLASH program address register,         RW,  Address offset: 0x24c  */
    __IO uint32_t PROG_DATA;            /*!< EFLASH program data register,            RW,  Address offset: 0x250  */
    __IO uint32_t ERASE_CTRL;           /*!< EFLASH erase register,                   RW,  Address offset: 0x254  */
    __IO uint32_t TIME_REG0;            /*!< EFLASH time register0,                   RW,  Address offset: 0x258  */
    __IO uint32_t TIME_REG1;            /*!< EFLASH time register1,                   RW,  Address offset: 0x25c  */
    __IO uint32_t NVR_PASSWORD;         /*!< EFLASH NVR password register,            RW,  Address offset: 0x260  */
    __IO uint32_t MAIN_PASSWORD;        /*!< EFLASH MAIN password register,           RW,  Address offset: 0x264  */
    __IO uint32_t CRC_ADDR;             /*!< EFLASH CRC DMA address register,         RW,  Address offset: 0x268  */
    __IO uint32_t CRC_LEN;              /*!< EFLASH CRC DMA length register,          RW,  Address offset: 0x26c  */    
    __IO uint32_t CRC_OUT;              /*!< EFLASH CRC OUT register,                 RW,  Address offset: 0x270  */
    __IO uint32_t MODE;                 /*!< EFLASH mode status register,             RO,  Address offset: 0x274  */
    __IO uint32_t STA0;                 /*!< EFLASH mode status register,             RO,  Address offset: 0x278  */
    __IO uint32_t STA1;                 /*!< EFLASH mode error register,              RO,  Address offset: 0x27c  */
    __IO uint32_t CFG_SECTOR;           /*!< EFLASH MAIN User configuration sector,   RO,  Address offset: 0x280  */
} EFLASH_TypeDef;  

/**
  * @brief Comparator controller
  */
//typedef struct {
//    __IO uint32_t CON0  ;
//    __IO uint32_t CON1  ;
//    __IO uint32_t STA  ;
//    __IO uint32_t CLR  ;

//} COMP_TypeDef;

/**
  * @brief DAC controller
  */
//typedef struct {
//    __IO uint32_t CON;
//} DAC_TypeDef;

/**
  * @brief OPAM controller
  */
//typedef struct {
//    __IO uint32_t CON;
//} OPAM_TypeDef;

//typedef struct{
//    __IO uint32_t LED_CON0; 
//    __IO uint32_t LED_CON1;
//    __IO uint32_t LED_CON2;
//    __IO uint32_t LED_BADR;
//}LED_TypeDef;

/**
  * @brief LCD
  */
typedef struct
{
    __IO uint32_t LCD_CON;
    __IO uint32_t LCD_COM_NUM;
    __IO uint32_t LCD_REFRESH;
    __IO uint32_t LCD_DIV_CON;
    __IO uint32_t LCD_COM_SEG_ENA;
    __IO uint32_t LCD_COM0_SEG;
    __IO uint32_t LCD_COM1_SEG;
    __IO uint32_t LCD_COM2_SEG;
    __IO uint32_t LCD_COM3_SEG;
    __IO uint32_t LCD_STA;
}LCD_TypeDef;

/**
  * @brief RTCC
  */
//typedef struct
//{
//    __IO uint32_t CR;
//    __IO uint32_t TIME; 
//    __IO uint32_t DATE;
//    __IO uint32_t STA;
//    __IO uint32_t ALRM0;
//    __IO uint32_t ALRM1;
//    __IO uint32_t COMPE;
//    __IO uint32_t TSTIME; 
//    __IO uint32_t TSDATE;
//}RTCC_TypeDef;

typedef struct{
    __IO uint32_t LVD_CON;
    __IO uint32_t LVD_CON1;
    __IO uint32_t LVD_CON2;
} LVD_TypeDef; 
/** 
  * @biref fadc
  */
//typedef struct {
//    __IO uint32_t   FADCCON0        ;// 0x00
////    __IO uint32_t   FADCACSCON      ;// 0x04
////    __IO uint32_t   FADCACSDAT      ;// 0x08
//    __IO uint32_t   FADCINT0        ;// 0x04
//    __IO uint32_t   FADCFLAG        ;// 0x08
//    __IO uint32_t   FADCDCOFFSET0   ;// 0x0c
//    __IO uint32_t   FADCDCOFFSET1   ;// 0x10
//    __IO uint32_t   FADCDMACON0     ;// 0x14
//    __IO uint32_t   FADCDMACON1     ;// 0x18
//    __IO uint32_t   FADCDMACON2     ;// 0x1c
//    __IO uint32_t   FADCDMACON3     ;// 0x20
//    __IO uint32_t   FADCDMACON4     ;// 0x24
//    __IO uint32_t   FADCDMACON5     ;// 0x28
//    __IO uint32_t   FADCDMACON6     ;// 0x2c
//    __IO uint32_t   FADCDMACON7     ;// 0x30
//    __IO uint32_t   FADCPPROC1CON0  ;// 0x34
//    __IO uint32_t   FADCPPROC1CON1  ;// 0x38
//    __IO uint32_t   FADCPPROC1CON2  ;// 0x3c
//    __IO uint32_t   FADCPPROC1CON3  ;// 0x40
//    __IO uint32_t   FADCPPROC1CON4  ;// 0x44
//    __IO uint32_t   FADCPPROC1CON5  ;// 0x48
//    __IO uint32_t   FADCPPROC1CON6  ;// 0x4c
//    __IO uint32_t   FADCPPROC1CON7  ;// 0x50
//    __IO uint32_t   FADCRES0        ;// 0x54
//    __IO uint32_t   FADCRES1        ;// 0x58
//    __IO uint32_t   FADCRES2        ;// 0x5c
//    __IO uint32_t   FADCRES3        ;// 0x60
//    __IO uint32_t   FADCSFRANACON0  ;// 0x64
//    __IO uint32_t   FADCSFRANACON1  ;// 0x68   
//    __IO uint32_t   FADCSFRADCCON0  ;// 0x6c   
//    __IO uint32_t   FADCSFRSOCCON0  ;// 0x70   
//    __IO uint32_t   FADCSFRSOCCON1  ;// 0x74   
//    __IO uint32_t   FADCSFRSOCCON2  ;// 0x78   
//    __IO uint32_t   FADCSFRSOCFLAG  ;// 0x7c   
//    __IO uint32_t   FADCSFRCALIB0   ;// 0x80   
//    __IO uint32_t   FADCSFRCALIB1   ;// 0x84   
//    __IO uint32_t   FADCSFRWCOEF0   ;// 0x88   
//    __IO uint32_t   FADCSFRWCOEF1   ;// 0x8c   
//    __IO uint32_t   FADCSFRWCOEF2   ;// 0x90   
//    __IO uint32_t   FADCSFRWCOEF3   ;// 0x94   
//    __IO uint32_t   FADCSFRWCOEF4   ;// 0x98   
//    __IO uint32_t   FADCSFRWCOEF5   ;// 0x9c    
//    __IO uint32_t   FADCSFRWCOEF6   ;// 0xa0    
//    __IO uint32_t   FADCSFRWCOEF7   ;// 0xa4   
//    __IO uint32_t   FADCSFRWCOEF8   ;// 0xa8   
//    __IO uint32_t   FADCSFRWCOEF9   ;// 0xac   
//    __IO uint32_t   FADCSFRWCOEF10  ;// 0xb0   
//    __IO uint32_t   FADCSFRWCOEF11  ;// 0xb4   
//    __IO uint32_t   FADCSFRWCOEF12  ;// 0xb8   
//} FADC_TypeDef;  

/**
  * @}
  */

/** @addtogroup Peripheral_memory_map
  * @{
  */
/*! FLASH base address in the alias region */
#define FLASH_BASE              ((uint32_t)0x00000000)
/*! SRAM base address in the alias region */
#define SRAM_BASE               ((uint32_t)0x20000000)
/*! Peripheral base address in the alias region */
#define PERIPH_BASE             ((uint32_t)0x40000000)

//--------------Peripheral memory map------------------//
#define APB0_BASE               PERIPH_BASE
#define APB1_BASE               (PERIPH_BASE + 0x10000)
#define MIX_BASE                (PERIPH_BASE + 0x20000)

#define SYSCTRL_BASE            (MIX_BASE + 0x000)
#define GPIOA_BASE              (MIX_BASE + 0x0A0)
#define GPIOB_BASE              (MIX_BASE + 0x0E0)
#define LVD_BASE                (MIX_BASE + 0x120)
#define ADC_BASE                (MIX_BASE + 0x140)
#define PLLFRAC_BASE            (MIX_BASE + 0x180)
#define WDT_BASE                (MIX_BASE + 0x190)
#define TIMER0_BASE             (MIX_BASE + 0x1A0)
#define TIMER_ALL_BASE          (MIX_BASE + 0x1C8)
#define TIMER1_BASE             (MIX_BASE + 0x1E0)
#define CRC_BASE                (MIX_BASE + 0x210)
#define EFLASH_BASE             (MIX_BASE + 0x240)
#define UART0_BASE              (MIX_BASE + 0x290)
#define UART1_BASE              (MIX_BASE + 0x2A0)
#define SPI0_BASE               (MIX_BASE + 0x2C0)
//#define SPI1_BASE               (MIX_BASE + 0x4500)
#define UST0_BASE               (MIX_BASE + 0x2E0)
#define TIMER4_BASE             (MIX_BASE + 0x310)
#define TK_BASE                 (MIX_BASE + 0x340)
#define LCD_BASE                (MIX_BASE + 0x3D0)
//#define OPAM_BASE               (MIX_BASE + 0x230)

#define SYSCTRL                 ((SYSCTRL_TypeDef *) SYSCTRL_BASE)
#define GPIOA                   ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB                   ((GPIO_TypeDef *) GPIOB_BASE)
#define LVD                     ((LVD_TypeDef *) LVD_BASE)
#define ADC                     ((ADC_TypeDef *)ADC_BASE)
#define PLLFRAC                 ((FPLL_TypeDef *)PLLFRAC_BASE)
#define WDT                     ((WDT_TypeDef *) WDT_BASE)
#define TIMER0                  ((TIMER_TypeDef *) TIMER0_BASE)
#define TIMER_ALL               ((TIMER_ALL_TypeDef *) TIMER_ALL_BASE)
#define TIMER1                  ((TIMER_TypeDef *) TIMER1_BASE)
#define CRC                     ((CRC_TypeDef *) CRC_BASE)
#define EFLASH                  ((EFLASH_TypeDef *) EFLASH_BASE)
#define UART0                   ((UART_TypeDef *) UART0_BASE)
#define UART1                   ((UART_TypeDef *) UART1_BASE)
#define SPI0                    ((SPI_IIC_TypeDef *) SPI0_BASE)
//#define SPI1                    ((SPI_IIC_TypeDef *) SPI1_BASE)
#define UST0                    ((UST_TypeDef *) UST0_BASE)
#define TIMER4                  ((TIMER_TypeDef *) TIMER4_BASE)
#define LCD                     ((LCD_TypeDef *) LCD_BASE)
//#define OPAM                    ((OPAM_TypeDef *) OPAM_BASE)

#define PA                      ((GPIO_TypeDef *) GPIOA_BASE)
#define PB                      ((GPIO_TypeDef *) GPIOB_BASE)
#define TIM0                    ((TIMER_TypeDef *) TIMER0_BASE)
#define TIM_ALL                 ((TIMER_ALL_TypeDef *) TIMER_ALL_BASE)
#define TIM1                    ((TIMER_TypeDef *) TIMER1_BASE)
#define TIM4                    ((TIMER_TypeDef *) TIMER4_BASE)

/**
  * @}
  */

#define     SYSCTRL_REG_OPT(expression)       {SYSCTRL->SYS_KEY = 0x3fac87e4; expression; SYSCTRL->SYS_KEY = 0;}

#ifdef __cplusplus
}
#endif

#endif /* __TS32F020X_H */

/**
  * @}
  */

  /**
  * @}
  */

/*************************** (C) COPYRIGHT 2022 JUSHENG ***** END OF FILE *****/
